Parallel processing headache

I'm having a splitting headache. It probably comes from the fact that I've been working on my AE68 for too long now. Processor design is an exercise in parallel processing. As the AE68 is capable of executing up to 6 instructions (with pipelining) at the same time, I need to keep track of all the instructions in flight. All that is giving me a splitting headache. My previous designs do not have as much ILP (Instruction Level Parallelism) as this beast. The AE18 executes 2 instructions at a time, while the AEMB executes 3 instructions at a time. Headache!!

I've been contemplating a while about writing a short series of blogs on hardware design. I'm wondering if it's a good idea as there aren't many instructional sites that show you how to do hardware design. Even the books are not sufficient and they often end up teaching you methods that cannot be implemented in the real world. I know that many of me readers don't read my technical blogs. So, if anyone is at all interested in reading about hardware design, please leave me some comments.

Anyway, I think that I'll stop working on the AE68 for a while. I'll get back to doing some other things (like work on my research project) instead and work on it over the weekends. I've already got most of the design down on paper. However, actually implementing it will probably take a little bit more time. Verification is going to be a nightmare and I'm already beginning to dread it. Well, hopefully, I'll be able to sign up a few volunteers to help me test and verify the processor, like for my previous designs.

*** Image shows a classic RISC pipeline with 5 instructions in-flight. ***