AE18 finished (sort of)

It didn't take quite long as it did the first time around. I've maximally finished the new AE18 core and uploaded it to the opencores cvs. It took just under a week to finish the core. I use the word "maximally" finished because it has reached the point where it works for all the tests that I wrote for it. So, barring other people finding any other bugs, it's working.

Also, there are still improvements that can be made to the core, i.e. optimisation. There are plenty of parts of the FPGA that can be optimised to be faster/smaller as I was only concerned with functionality initially. I was designing it from scratch without much to go on. So, I was mainly concerned with correct functionality.

Also, I have yet to verify that the core actually works in hardware as I do not have access to an FPGA at the moment. So, It's only simulation proven. So, I cannot warranty it against any other hardware problems and I do not yet know how well it will actually perform in hardware. However, I am confident that unless other bugs show up, it should work properly.

If anyone is wondering what processor design entails, the image shows a snapshot of, what we call, a timing diagram. Basically, I stare at miles and miles worth of timing diagrams to make sure that everything is workng correctly. Things are going 1/0 when they should. If something doesn't work, I fix the design and check it again.

Through this exercise, I have learned a few things. I've discovered that my chip design skills and processor architecture knowledge have improved tremendously over the last few years. Also, I've made changes to my processor design steps to make processor design even easier. Now, I hope that these things translate well to my research project.

http://www.opencores.org/projects/ae18

UPDATE: I had thought of starting my aeMB rewrite project today, but my brain is over saturated. A German company has shown some interest in using the aeMB. However, I guess I'll do something else today.