Tuesday, December 11, 2007

AEMB Virtual Ethernet MAC Madness

An ethernet MAC is the device inside a computer that provides the interface to an ethernet network. An example open source ethernet MAC consumes about 2800 slices in an FPGA. My new AEMB design only uses up about 1500 slices. It doesn't seem very logical to integrate a MAC that is almost twice the size of a processor, in order to make it ethernet capable.

So, if someone is interested in building an embedded application with an ethernet connection, they can either:

  1. Use an off-the-shelf ethernet MAC like the RTL81XX series of chips and stick it on the board. These come in a variety of bus interfaces to communicate with different processors. Then, they can write a low level software driver to drive this chip. The typical interface is either ISA (8-bit mode) or PCI (32-bit mode). There are a variety of vendors for these chips.
  2. Integrate a MAC into their processor and interface it to a PHY. There are quite a few embedded processor coming onto the market today that integrate a single built in MAC. Even little 8-bit controllers from Microchip have built in ethernet capabilities. Everyone needs an Internet capable toaster. The programmer treats it in much the same way as any other built in device of the micro controller, and write software to control it.
  3. Try to do something truly crazy, and implement a virtual MAC in software!
I've just been toying around with the idea of a virtual software MAC. I'm thinking of this in terms of using it with the AEMB. I can be quite certain that the AEMB can run at above 100MHz. This gives it about 50MIPS per thread. So, the question is simply, whether or not there is enough software power to implement a software MAC.

I started investigating a couple of different PHYs. I checked out the RTL8201 and LAN8700 chips. Regular PHY chips use the MII interface which is a defined standard (IEEE 802.3u). So, if a MAC (virtual or otherwise) conforms to this standard, it will be able to interface with most industry PHYs. So, reading the technical data-sheets, I find that the transfer interface is fairly simple. For a 10BaseT MII interface, the data is transferred in 4-bit nibbles at 2.5 MHz!


This is most certainly doable in software with a 50MIPS thread, if the software is written well and the hardware interface carefully defined. A 50MIPS thread can potentially bit-bang at a maximum rate of 12.5MHz. So, it seems that it is potentially possible to implement an entire ethernet chip in software! I'm so excited. Now, if I can only split myself into two so that one can work on this while the other works on my PhD!

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